devices incorporated lf2242 12/16-bit half-band interpolating/ decimating digital filter video imaging products 1 08/16/2000Clds.2242-k lf2242 12/16-bit half-band interpolating/ decimating digital filter devices incorporated q q q q q 40 mhz clock rate q q q q q passband (0 to 0.22 f s ) ripple: 0.02 db q q q q q stopband (0.28 f s to 0.5 f s ) rejection: 59.4 db q q q q q user-selectable 2:1 decimation or 1:2 interpolation q q q q q 12-bit twos complement input and 16-bit output with user-selectable rounding, 8- to 16-bits q q q q q user-selectable twos complement or inverted offset binary output formats q q q q q three-state outputs q q q q q replaces trw/ raytheon/ fairchild tmc2242 q q q q q package styles available: ? 44-pin plcc, j-lead ? 44-pin pqfp features description the lf2242 is a linear-phase, half- band (low pass) interpolating/ decimating digital filter that, unlike intricate analog filters, requires no tuning. the lf2242 can also signifi- cantly reduce the complexity of traditional analog anti-aliasing pre- filters without compromising the signal bandwidth or attenuation. this can be achieved by using the lf2242 as a decimating post-filter with an a/d converter and by sampling the signal at twice the rate needed. likewise, by using the lf2242 as an interpolating pre-filter with a d/a converter, the corresponding analog reconstruction post-filter circuitry can be simplified. the coefficients of the lf2242 are fixed, and the only user programming required is the selection of the mode (interpolate, decimate, or pass- through) and rounding. the asyn- chronous three-state output enable control simplifies interfacing to a bus. data can be input into the lf2242 at a rate of up to 40 million samples per second. within the 40 mhz i/o limit, the output sample rate can be one- half, equal to, or two times the input sample rate. once data is clocked in, the 55-value output response begins after 7 clock cycles and ends after 61 clock cycles. the pipeline latency from the input of an impulse response to its corresponding output peak is 34 clock cycles. the output data may be in either twos complement format or inverted offset binary format. to avoid truncation errors, the output data is always internally rounded before it is latched into the output register. rounding is user-selectable, and the output data can be rounded from 16 bit values down to 8 bit values. dc gain of the lf2242 is 1.0015 (0.0126 db) in pass-through and decimate modes and 0.5007 (C3.004 db) in interpolate mode. passband ripple does not exceed 0.02 db from 0 to 0.22 f s with stopband attenuation greater than 59.4 db from 0.28 f s to 0.5 f s (nyquist frequency). the response of the filter is C6 db at 0.25 f s . full compliance with ccir recom- mendation 601 (C12 db at 0.25 f s ) can be achieved by cascading two devices serially. lf2242 b lock d iagram oe to all registers si 11C0 interpolation circuit 55-tap fir filter round and limit circuit decimation circuit 16 3 3 rnd 2C0 tco so 15C0 3 3 sync int dec clk 16 12 12
devices incorporated lf2242 12/16-bit half-band interpolating/ decimating digital filter video imaging products 2 08/16/2000Clds.2242-k controls int interpolation control when int is low and dec is high (table 1), the device internally forces every other incoming data sample to zero. this effectively halves the input data rate and the output amplitude. dec decimation control when dec is low and int is high (table 1), the output register is strobed on every other rising edge of clk (driven at half the clock rate), decimating the output data stream. f igure 1. f requency r esponse of f ilter signal definitions power v cc and gnd +5 v power supply. all pins must be connected. clock clk master clock the rising edge of clk strobes all regis- ters. all timing specifications are refer- enced to the rising edge of clk. sync synchronization control incoming data is synchronized by hold- ing sync high on clk n , and then by bringing sync low on clk n+1 with the first word of input data. sync is held low until resynchronization is desired, or it can be toggled at half the clock rate. for interpolation (int = low), input data should be presented at the first ris- ing edge of clk for which sync is low and then at every alternate rising edge of clk thereafter. sync is inactive if dec and int are equal (pass-through mode). inputs si 11C0 data input 12-bit twos complement data input port. data is latched into the register on the rising edge of clk. the lsb is si 0 (figure 2). outputs so 15-0 data output the current 16-bit result is available on the so 15-0 outputs. the lf2242s limiter ensures that a valid full-scale (7fff positive or 8000 negative) output will be generated in the event of an internal overflow. the lsb is so 0 (figure 2). 0 0.1 | s 0.2 | s 0.3 | s 0.4 | s 0.5 | s frequency (normalized) 0 C10 C20 C30 C40 C50 C60 C70 C80 gain (db) int dec mode 0 0 pass-through* 0 1 interpolate 1 0 decimate 1 1 pass-through* *input and output registers run at full clock rate t able 1. m ode s election
devices incorporated lf2242 12/16-bit half-band interpolating/ decimating digital filter video imaging products 3 08/16/2000Clds.2242-k rnd 2-0 rounding control the rounding control inputs set the posi- tion of the effective lsb of the output data by adding a rounding bit to the internal bit position that is one below that speci- fied by rnd 2-0 . all bits below the effec- tive lsb position are subsequently ze- roed (table 2). tco twos complement format control the tco input determines the format of the output data. when tco is high, the output data is presented in twos comple- ment format. when tco is low, the data is in inverted offset binary format (all output bits are inverted except the msb the msb is unchanged). oe output enable when the oe signal is low, the current data in the output register is available on the so 15-0 pins. when oe is high, the outputs are in a high-impedance state. f igure 2. i nput and o utput f ormats rnd 2-0 so 15 so 14 so 13 so 12 ? ? ? so 8 so 7 so 6 so 5 so 4 so 3 so 2 so 1 so 0 000xxxx ? ? ? xxxxxxxxr 001xxxx ? ? ? xxxxxxxr0 010xxxx ? ? ? xxxxxxr0 0 011xxxx ? ? ? xxxxxr00 0 100xxxx ? ? ? xxxxr0 00 0 101xxxx ? ? ? xxxr00000 110xxxx ? ? ? xxr000000 111xxxx ? ? ? xr0000000 'r' indicates the half-lsb rounded bit (effective lsb position) t able 2. r ounding f ormat twos complement input format twos complement output format (tco = 1, non-interpolate) twos complement output format (tco = 1, interpolate) inverted offset binary output format (tco = 0, non-interpolate) inverted offset binary output format (tco = 0, interpolate) 10 9 8 2 1 0 11 3 C2 0 2 C1 2 C2 2 C8 2 C9 2 C10 2 C3 2 C11 (sign) 14 13 12 2 1 0 15 3 C2 0 2 C1 2 C2 2 C12 2 C13 2 C14 2 C3 2 C15 (sign) 14 13 12 2 1 0 15 3 C2 1 2 0 2 C1 2 C11 2 C12 2 C13 2 C2 2 C14 (sign) 14 13 12 2 1 0 15 3 2 0 2 C1 2 C2 2 C12 2 C13 2 C14 2 C3 2 C15 (sign) 14 13 12 2 1 0 15 3 2 1 2 0 2 C1 2 C11 2 C12 2 C13 2 C2 2 C14 (sign)
devices incorporated lf2242 12/16-bit half-band interpolating/ decimating digital filter video imaging products 4 08/16/2000Clds.2242-k storage temperature ........................................................................................................... C65c to +150c operating ambient temperature ........................................................................................... C55c to +125c v cc supply voltage with respect to ground ............................................................................ C0.5 v to +7. 0v input signal with respect to ground ............................................................................... C0.5 v to v cc + 0.5 v signal applied to high impedance output ...................................................................... C0.5 v to v cc + 0.5 v output current into low outputs ................................................................................................ ............. 25 ma latchup current ................................................................................................................ ............... > 400 ma m aximum r atings above which useful life may be impaired (notes 1, 2, 3, 8) o perating c onditions to meet specified electrical and switching characteristics mode temperature range (ambient) supply voltage active operation, commercial 0c to +70c 4.75 v v cc 5.25 v active operation, industrial -40c to +85c 4.75 v v cc 5.25 v symbol parameter test condition min typ max unit v oh output high voltage v cc = min., i oh = C2.0 ma 2.4 v v ol output low voltage v cc = min., i ol = 4.0 ma 0.4 v v ih input high voltage 2.0 v cc v v il input low voltage (note 3) 0.0 0.8 v i ix input current ground v in v cc (note 12) 10 a i oz output leakage current (note 12) 10 a i cc1 v cc current, dynamic (notes 5, 6) 80 ma i cc2 v cc current, quiescent (note 7) 10 ma c in input capacitance t a = 25c, f = 1 mhz 10 pf c out output capacitance t a = 25c, f = 1 mhz 10 pf e lectrical c haracteristics over operating conditions (note 4)
devices incorporated lf2242 12/16-bit half-band interpolating/ decimating digital filter video imaging products 5 08/16/2000Clds.2242-k lf2242C 33 25 symbol parameter min max min max t cyc cycle time 33 25 t pw clock pulse width 10 10 t s input setup time 10 8 t h input hold time 0 0 t d output delay 20 16 t dis three-state output disable delay (note 11) 15 15 t ena three-state output enable delay (note 11) 15 15 switching characteristics c ommercial o perating r ange (0c to +70c) notes 9, 10 (ns) s witching w aveforms :p ass -t hrough m ode (int = dec) clk t dis si 11-0 so 15-0 oe n t s t pw 123 7 sync n+1 n+2 t h 8910 high impedance t ena t d f( n )f( n+1 )f( n+2 ) t pw
devices incorporated lf2242 12/16-bit half-band interpolating/ decimating digital filter video imaging products 6 08/16/2000Clds.2242-k s witching w aveforms :i nterpolate m ode (int = 0, dec = 1) clk t dis si 11-0 so 15-0 oe n t s t pw 123 7 sync n+2 t h 8910 high impedance t ena t d f( n )f( n+1 )f( n+2 ) t pw s witching w aveforms :d ecimate m ode (int = 1, dec = 0) clk t dis si 11-0 so 15-0 oe t pw 123 7 sync n+1 n+2 8910 high impedance t ena t d f( n )f( n+2 ) n t h t s t pw
devices incorporated lf2242 12/16-bit half-band interpolating/ decimating digital filter video imaging products 7 08/16/2000Clds.2242-k 1. maximum ratings indicate stress specifications only. functional oper- ation of these products at values beyond those indicated in the operating condi- tions table is not implied. exposure to maximum rating conditions for ex- tended periods may affect reliability. 2. the products described by this spec- ification include internal circuitry de- signed to protect the chip from damag- ing substrate injection currents and ac- cumulations of static charge. neverthe- less, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 3. this device provides hard clamping of transient undershoot and overshoot. in- put levels below ground or above v cc will be clamped beginning at C0.6 v and v cc + 0.6 v. the device can withstand indefinite operation with inputs in the range of C0.5 v to +7.0 v. device opera- tion will not be adversely affected, how- ever, input current levels will be well in excess of 100 ma. 4. actual test conditions may vary from those designated but operation is guar- anteed as specified. 5. supply current for a given applica- tion can be accurately approximated by: where n = total number of device outputs c = capacitive load per output v = supply voltage f = clock frequency 6. tested with all outputs changing ev- ery cycle and no load, at a 20 mhz clock rate. 7. tested with all inputs within 0.1 v of v cc or ground, no load. 8. these parameters are guaranteed but not 100% tested. ncv f 4 2 notes 9. ac specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 v (except t dis test), and input levels of nominally 0 to 3.0 v. output loading may be a resistive divider which provides for specified i oh and i ol at an output voltage of v oh min and v ol max respectively. alternatively, a diode bridge with upper and lower current sources of i oh and i ol respectively, and a balancing voltage of 1.5 v may be used. parasitic capacitance is 30 pf minimum, and may be distributed. this device has high-speed outputs ca- pable of large instantaneous current pulses and fast turn-on/turn-off times. as a result, care must be exercised in the testing of this device. the following measures are recommended: a. a 0.1 f ceramic capacitor should be installed between v cc and ground leads as close to the device under test (dut) as possible. similar capacitors should be installed between device v cc and the tester common, and device ground and tester common. b. ground and v cc supply planes must be brought directly to the dut socket or contactor fingers. c. input voltages should be adjusted to compensate for inductive ground and v cc noise to maintain required dut input levels relative to the dut ground pin. 10. each parameter is shown as a min- imum or maximum value. input re- quirements are specified from the point of view of the external system driving the chip. setup time, for example, is specified as a minimum since the exter- nal system must supply at least that much time to meet the worst-case re- quirements of all parts. responses from the internal circuitry are specified from the point of view of the device. output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 11. for the t ena test, the transition is measured to the 1.5 v crossing point with datasheet loads. for the t dis test, the transition is measured to the 200mv level from the measured steady-state output voltage with 10ma loads. the balancing volt- age, v th , is set at 3.5 v for z-to-0 and 0-to-z tests, and set at 0 v for z- to-1 and 1-to-z tests. 12. these parameters are only tested at the high temperature extreme, which is the worst case for leakage current. s1 i oh i ol v th c l dut oe 0.2 v t dis t ena 0.2 v 1.5 v 1.5 v 3.5v vth 1 z 0 z z 1 z 0 1.5 v 1.5 v 0v vth v ol * v oh * v ol * v oh * measured v ol with i oh = C10ma and i ol = 10ma measured v oh with i oh = C10ma and i ol = 10ma f igure b. t hreshold l evels f igure a. o utput l oading c ircuit
devices incorporated lf2242 12/16-bit half-band interpolating/ decimating digital filter video imaging products 8 08/16/2000Clds.2242-k so 12 so 11 so 10 so 9 so 8 gnd v cc so 7 so 6 so 5 so 4 so 13 so 14 so 15 oe tco dec int sync clk gnd si 11 gnd v cc si 10 si 9 si 8 si 7 si 6 si 5 si 4 si 3 v cc 33 32 31 30 29 28 27 26 25 24 23 top view 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 so 3 so 2 so 1 so 0 rnd 2 rnd 1 rnd 0 si 0 si 1 si 2 gnd 12 13 14 15 16 17 18 19 20 21 22 44-pin ordering information 44 1 2 3 4 5 6 39 38 37 36 35 34 33 32 31 30 29 43 42 41 40 25 24 26 27 28 19 18 20 21 22 23 7 8 9 10 11 12 13 14 15 16 17 top view so 12 so 11 so 10 so 9 so 8 gnd v cc so 7 so 6 so 5 so 4 gnd v cc si 10 si 9 si 8 si 7 si 6 si 5 si 4 si 3 v cc so 3 so 2 so 1 so 0 rnd 2 rnd 1 rnd 0 si 0 si 1 si 2 gnd so 13 so 14 so 15 oe tco dec int sync clk gnd si 11 44-pin speed 33 ns 25 ns plastic j-lead chip carrier (j1) LF2242JC33 lf2242jc25 0c to +70c c ommercial s creening plastic quad flatpack (q4) lf2242qc33 lf2242qc25 C40c to +85c c ommercial s creening
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